Non-volatile flash memory cells are known to be formed by a transistor structure comprising a channel that is located between source and drain and controlled by a control gate electrode, and a floating gate electrode that is provided as storage means. NAND arrays of flash memories having memory cells with floating gate are, for instance, described in Y.-S. Yim et al., “70 nm NAND Flash Technology with 0.025 μm2 Cell Size for 4 Gb Flash Memory” in IEDM 2003, Session 34.1.
More particularly, each of the flash memory cells comprises a transistor body of semiconductor material, which is limited on two opposing sides by electrically insulating material of shallow trench isolations (STIs). An upper surface of the transistor body is planar and covered with a dielectric material, which is provided as tunneling oxide. Above the tunneling oxide, the floating gate electrode made of electrically conductive material is arranged that is surrounded by dielectric material and thus completely electrically insulated. A control gate electrode is arranged above the floating gate electrode and capacitively coupled to the floating gate electrode by a coupling dielectric layer inbetween the floating gate and control gate electrodes. The inter-gates coupling dielectric layer typically is made of an oxide-nitride-oxide (ONO) structure and includes first, second and third layers of silicon oxide, silicon nitride and silicon oxide, respectively. Programming or erasing of flash memory cells may, for instance, be based on Fowler-Nordheim tunneling through the tunneling oxide layer between the floating gate electrode and the semiconductor body.
In a typical NAND array of flash memory cells, control gate lines (or word lines) forming or contacting the control gate electrodes of the flash memory cells cross over STIs. Furthermore, bit lines are arranged above the control gate lines isolated therefrom and in parallel alignment to STIs (crossing the control gate lines) which are electically contacting the semiconductor substrate active regions.
Now referring to FIG. 1, a schematic top-down view of a typical NAND-type flash memory cell array is shown, where memory cells are arranged in rows and columns. Each NAND string that comprises a series connection of plural memory cells, typically 32, and two selection transistors is interconnected between a bit line contact BC and a common ground (source) line SL running in the x-direction. Crossing bit lines that run in the y-direction and define columns, a plurality of word lines WL and two selection transistor lines, namely a source line sided selection transistor line SSL and a bit line sided selection transistor line BLS, that run in x-direction and defining rows are arranged, where memory cell control gate electrodes are connected to the word lines and selection transistor control gate electrodes are connected to the selection transistor lines. Between adjacent bit lines, bit line pitch F may be identified.
Reference is made to FIG. 2, depicting a partial schematic cross-sectional view of the conventional NAND memory cell array of FIG. 1, which section is taken along line I-I (x-direction) of FIG. 1. In a typical manufacturing method thereof, on a semiconductor substrate 1 (or body) provided with active structures separated by shallow trench isolations 2 a tunneling oxide layer 6 is deposited on an upper surface of the substrate, followed by a deposition of a floating gate layer on the tunneling oxide layer 6. Then, the floating gate layer is structured using conventional lithography steps and etched to prepare floating gate lines in parallel alignment to bit lines to be prepared. As is typical, floating gate lines are merely structured in a region of memory cells to be prepared thus leaving the floating gate layer unstructured in regions of selection transistor lines and source lines to be prepared based on the fact that in conventional processing floating gate electrode level is used for manufacturing selection transistor control gate electrodes, which, however, requires to not interrupt selection transistor lines intended to run in a direction crossing the floating gate lines. After deposition of a coupling dielectric layer 7 on the floating gate lines and unstructured remnants of the floating gate layer, deposition of a word line layer follows that is structured to prepare word lines running in a direction crossing the floating gate lines. Structuring the word lines, etching proceeds to thereby create isolated floating gate electrodes. Also, yet unstructured regions of the floating gate layer are structured to create the selection transistor lines and allow later on to create source lines. The source lines are typically made in a separate step by filling polysilicon into grooves of planarized interlevel dielectric. Hence, referring to FIG. 2, in conventional processing a source line sided selection transistor line SSL is created above the tunneling oxide layer 6, and, a “word line” (without any function) out of the word line layer is created on the coupling dielectric layer 7. Then, metallic line 5 is formed which is in electrical contact with the SSL by providing electric contact 3. In order to suppress undesired effects based on capacitive coupling, it is usual to electrically connect metallic line 5 to conductive line “WL”.
Accordingly, selection transistor lines manufactured in floating gate line level typically consist of polysilicon thus having an undesired high electrical resistivity. Apparently, using conventional processing steps, it is not possible to reduce the high electric resistivity thereof as typically is done in the case of word lines where metallic layers such as WSi are deposited on polysilicon.